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Name: Ellie
Status: student
Grade: 9-12
Location: IL
Country: USA
Date: Fall 2013


Question:
We have been learning about computer chips in our materials science class. There is a photo process for creating components, wiring, etc. on the chip. These are very small and high resolution. At this size scale, how is diffraction in the photo process avoided? How is capacitance of parallel wires corrected?



Replies:
Ellie,

You have hit on two big problems in the chip industry as it marches continuously to smaller sizes. Light does diffract around the edges of the mask, and it can create fuzzy patterns. One solution is to use light of shorter wavelength. Rather than using visible light (with wavelengths about 350-750nm), light with a shorter wavelength (e.g., ultraviolet or even x-rays) can reduce the diffraction. Another method is to use electrons to paint the mask patterns. Other methods exist, and each has its drawbacks, but mostly they try to overcome the limitations of diffraction that you pointed out.

As for capacitance, one of the major sources of problems with the capacitance is the switching transistors themselves. The capacitance can limit the switching speed of the transistors, and thus cause a fundamental limitation to the overall chip speed. Approaches have been devised to reduce this capacitance by, for example, floating the transistors within an insulator (Silicon on Insulator technology). Interconnect capacitances can similarly become a problem as high interconnect capacitance reduces signal speeds throughout the chip and lead to similar limitations in overall chip speed. Reductions in signal path length and keeping the signals that can cross-interfere are two typical ways to reduce the problems of line capacitance, but these tricks become harder to do as everything shrinks. One way to continue gains is to use three-dimensional chips to allow more transistors/volume. You have identified two very real problems in shrinking electronics, and many approaches are being pursued.

Kyle J. Bunch, PhD, PE


Hi Ellie,

There are several ways of avoiding diffraction. The older way was to position the photo-mask in direct physical contact to the photoresist layer that coats the silicon chip.

Another improved method is to use photo-masks several times larger than the chip, and use precision optics to project a diffraction-free miniature chip-size image onto the chip's photoresist layer. This method has a resolution down to about two microns.

More recently, with the size of the features being created that are so small that their size approaches (or is even smaller than) the wavelength of visible light, other methods of imaging the photoresist are used that do not involve the use of photo-masks and visible light. An example of this is the use of electron beam lithography, where an electron beam is used to directly expose the photoresist layer on the silicon.

Capacitance of parallel conductors on a chip is very small, since the distances where conductors run parallel, is also minute. Thus capacitance between parallel conductors on a chip is often insignificant. However, so-called "crosstalk" between parallel conductors can in some cases be a problem. During the design of a chip, the design and simulation software used can predict any problems and these can be corrected in the design stage.

Regards, Bob Wilson


Greetings Ellie,

You are correct! There are limiting factors in the process of microfabrication that are very much related to the wavelength of the light used. However, there are several tricks people have been developing over the years, such as a thin layer of water between the last conventional optic and the wafer. But ultimately the easiest trick, at least to understand, is that we should keep decreasing the wavelength. Currently we've progressed to UV at sub 200nm wavelengths (with features down to ~50nm) and even smaller patterning is possible through techniques that use either x-rays or electrons (which can have much smaller wavelengths).

I am not an expert on micro-fabrication, but they also tend to perform the etching in the "near-field" limit. Here the separation from the final optical element to the surface is much less than the wavelength of the light and the normal diffraction pattern has yet to develop. Also, while diffraction effects are possible if the wafer surface is far enough away, the relative intensity (and hence ability to etch) of the fringes is much less than the central cone. Hence the main limitation is one of attempting to focus beyond (smaller) than the fundamental diffraction spot size.

I hope things helps! Michael Pierce



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